SoC / FPGA Design

Our design team experienced in developing various products have strong problem-solving skills from developing micro-architecture for given specifications and solving issues till tape-outs.

Our Engineering team expertise in various stages of the design flow, Such as:

  • Micro-Architecture development for given specifications
  • SoC Design / ARM-based SoC architecture designs
  • RTL Integration & IP subsystem development
  • Full-Chip / SoC Level Design with Verilog, VHDL, System Verilog
  • Migration from FPGA to ASIC
  • Lint, CDC Checks and writing waivers
  • Integration of digital and analog blocks (Like SERDES PMA + PCS or DDR + Phy etc.,)
  • Synthesis, STA Constraints for both ASIC and FPGA
  • Logic equivalency and formality checks
  • Hands-on experience on Various Industrial EDA tools
  • Optimization of Power, Area and timing tradeoff
  • FPGA Prototyping on Xilinx / Altera FPGA Boards
Our Designers having experience in:
  • High-Speed protocol Interfaces like:
    • PCIe Gen1,2,3,4,5 With PIPE / SERDES
    • Ethernet 100G, 40G, 10G, 1G
    • USB 3.0, USB 2.0 host and device controllers
    • AXI, AHB
  • Other Interfaces like APB / SPI / UART /I2C
  • Multi Clock / Multi-Frequency Domain Designs
  • Mixed-signal IPs Integration such as:
    • ADC/DAC
    • PLLs
    • DDR PHY
    • DVI / HDMI
  • DDR Controllers
  • Integration of CPU Cores like ARM Cortex
  • Image Processing
The RTL Signoff could be a series of well-defined necessities that have to be met throughout the RTL phase of IC design and verification before moving on to the succeeding phase. The succeeding phase is often synthesis, followed by place & route. The justification for RTL Signoff is to create positives that the correct verification, checks, and fixes, are performed on the RTL, immediately within the flow, instead of waiting till they’re found throughout the later stages, leading to pricey retread.
Examples of RTL Signoff requirements include:
  • Verification of Structural Design Codes which includes false and multi-cycle paths.
  • Code and functional coverage with assertions level verification.
  • Linting for simulation and synthesis.
  • Through static and dynamic verification, verification of Clock and Reset domain.
  • Meeting the power goal which includes power estimation and reduction.
  • Verification of Voltage and Power Domain.
  • Unified Power Format(UPF) verification.
  • Inspection of Area, timing, and congestion for ensuring the physical clean RTL
Silverchips allows designers and DFT experts to catch “test-related” issues early in the design cycle, at RTL. It also allows the exploration of different DFT implementation options such as test points and estimates the impact on the design implementation steps. Silverchips helps make the right choices when it comes to DFT which saves time, effort as well as cost.
Key Features:
  • Absolute Rule Checks for DFT Design.
  • Can be entitled to running 3rd party ATPG at RTL.
  • Enhancement capabilities for following Test Coverage.
    • Clock / Reset controllability auto-fix.
    • Shadow logic insertion.
    • X generator analysis.
    • Test point insertion.
  • Specific ATPG aware test coverage evaluation.
  • Automated flow for compression exploration.
  • Support Unified Power Format-based checks at RTL.
  • Graphical User Interface.
    • Identify the root cause of DFT violations.
    • Test topology for low coverage debug.
  • Hierarchical DFT exploration based on Core Test Language (CTL) models.
  • Capability to create RTL with scan / Auto-fix logic