Feasibility report, micro-architecture, RTL coding – Verilog, SystemVerilog, Lint, CDC, Synth, STA .
FPGA porting of IP/system, FPGA specific optimization, Xilinx / Intel / MicroChip / Lattice specific porting and debugging expertise.
Test-plan and VE development and enhancement with SystemVerilog, UVM, IP/SoC level verification based on Coverage-driven directed and random tests.
Customer IP maintenance, end-customer support, system integration, application level logic updates, system level verification.
Pronesis Technologies provides services in areas of RTL development, FPGA implementation, Module and full-chip level verification, Pre and Post silicon validation, Verification IP development in Verilog, SystemVerilog using UVM, OVM, etc.
Pronesis Technologies provides all services in area of Physical Design. These services include Top and block level physical implementation, Analog block integratin, Floorplanning, Clock tree synthesis, Place & Route, Timing closure, Physical verification, IR Drop/EM/SI analysis and closure, etc.