In-house IP and VIP models for early SoC flow estimation. Silverchips CLI with agentic AI, covering UVM testbench generation through full pipeline verification. Full-SoC verification for RISC-V, sensor fusion, and NPU silicon.
Full-stack IP and VIP models covering RISC-V cores, chiplet interfaces, PCIe, CXL, UALink, UFS, standard buses, and common peripherals. Not compliance IP. Estimation IP, built so your architects can size the SoC, run the flow, and lock schedule before any third-party license closes.
The Silverchips CLI wraps our agentic AI models around the flow you already run. Feed it a YAML spec, point it at our VIP library, it assembles a complete UVM testbench. Point it at any netlist, it runs the full verification pipeline in one command, from RTL simulation through final board simulation with GDS-extracted parasitics.
We build full-SoC testbenches for automotive, sensor-fusion, and AI-compute silicon. RISC-V A-core, M-core, and S-core integration. Camera, radar, and lidar fusion executed at the model level inside the testbench. CNN and NPU workload coverage. Not IP-block toy tests. The workload your chip will actually run in the field.
Front-end to signoff. Take a project turnkey, augment an in-house team, or engage stage by stage. Onsite in Korea. Offsite globally.
Feasibility, micro-architecture, and RTL development. Verilog and SystemVerilog. Lint, CDC, synthesis, and STA closure through to netlist handoff.
Test-plan and environment development in SystemVerilog and UVM. IP and full-SoC verification, coverage-driven, directed and random. VIP-based bring-up and integration.
Top and block-level implementation. Floorplan, CTS, place and route, timing closure. Physical verification. IR-drop, EM, and SI analysis through signoff.
FPGA porting of IP and full systems. FPGA-specific optimization and debug. Prototyping and pre-silicon validation across major FPGA platforms.
Not all silicon is the same. These are the workloads and topologies where we've spent the most cycles and can move the fastest.
TCON, DDI, and mixed-signal integration for panel silicon. Deep experience with Korea's display ecosystem, across both DV and physical design.
Full-SoC verification for ADAS silicon with RISC-V multicore, sensor fusion, and safety workloads. Testbenches that stress the chip the way the road will.
CNN accelerators, NPU verification, and transformer workloads. Model-level testbenches that exercise the accelerator the way the network actually will.
A walkthrough of what happens between "silverchips gen-tb" and 42 files on disk, and why the input spec matters more than the model.
What breaks at the workload level that block-level UVM environments never surface, and how we build testbenches that catch it.
How the Silverchips CLI runs RTL sim, pin-level boardsim, post-synth GLS, post-PnR GLS, and final boardsim with GDS parasitics from a single verify invocation.
Architecture, verification, physical design, signoff. Bring us the idea, we bring the team, the flow, and the CLI.