Four workloads where Silverchips has spent the most cycles and can move fastest: ADAS silicon with sensor fusion at the core, RISC-V experimentation, Display IC, and NPU/CNN verification.
An ADAS SoC is not one problem. It is a multicore RISC-V system running safety-classified workloads, a neural network stack (CNN and NPU) executing perception at frame rate, and a sensor fusion engine reconciling all of it into decisions the vehicle acts on. Every one of those subsystems has to be verified against the workload it will actually run in the car. Block-level testing does not find the bugs that live at the boundary.
Silverchips builds full-SoC testbenches for automotive silicon. Camera, radar, lidar, and ultrasonic inputs are executed at the model level from our VIP library. The three RISC-V cores (application, management, safety) run their real firmware. The NPU and CNN accelerators process real workload traces. Sensor fusion, the crown jewel of the design, is exercised end to end.
RISC-V is not just an open ISA. It is a laboratory for architecture experimentation, and Silverchips is running experiments. Tightly-coupled accelerators as extra execution units inside the RISC-V pipeline. Custom instruction extensions in the reserved opcode space. Domain-specific dispatch. Reorder-buffer tracking of accelerator ops as first-class instructions. Zero DMA. Zero context switch. Everything in registers.
The result is compute density that a coprocessor sitting behind a bus can not match. Neural network layers, signal processing kernels, and cryptography primitives execute inline with regular instructions. The register file is the interface. The reorder buffer is the scheduler. The custom instruction is the API.
Display silicon is a tight envelope. Every pixel has to land inside a fixed timing window. Every panel ages differently. Traditional TCON and DDI chains solve this with lookup tables and static correction, then hope the panel behaves. That is not enough for modern panels.
A Neural TCON puts a small RISC-V core with a tightly-coupled NPU into the pixel pipeline. Per-pixel inference runs at pixel rate. Weights are updated over lifetime as the panel ages. The correction is not a lookup, it is a learned function. Same envelope. Same power budget. Better panel over Year 3, Year 5, Year 10.
An NPU or CNN accelerator can look flawless in a synthetic operator test and still fail on a real network. Layer boundaries, activation ranges, memory pressure, quantization edge cases, and pipelining hazards do not show up until you run the model the customer will actually deploy. Silverchips verifies accelerators at the workload level.
Our verification environment executes reference networks against the RTL, gathers per-operator coverage, and stresses the accelerator across the numerical range it will see in production. We build coverage bins for the operators, dataflow patterns, and quantization behavior that matter. Golden-model comparison at the tensor level, not just the register level.
ADAS, display, NPU, RISC-V experiment, chiplet system. Bring us the idea, we bring the team, the flow, and the CLI.