Engineering writing on the Silverchips CLI, full-SoC verification, physical design, and the corners of RISC-V experimentation where we spend our time. Real work, not takes.
A walkthrough of what happens between "silverchips gen-tb" and 42 files on disk, and why the input spec matters more than the model.
What breaks at the workload level that block-level UVM environments never surface, and how we build testbenches that catch it.
How the Silverchips CLI runs RTL sim, pin-level boardsim, post-synth GLS, post-PnR GLS, and final boardsim with GDS parasitics from a single verify invocation.
Bring us the idea, we bring the team, the flow, and the CLI.